1. Field of the Invention
The present invention relates to a flash memory, and more particularly, to a flash memory in which bit lines are precharged in a program operation.
2. Description of the Related Art
In a flash memory, a plurality of memory cells are connected to one word line and divided into pages by units of one or more word lines. The memory cells connected to one word line are connected to corresponding bit lines. A row decoder and a column decoder select word lines and bit lines, respectively. The flash memory performs an erase operation, a program (write) operation and a read operation. The memory cells arranged in the flash memory are a stacked gate type or a split gate type. Whether the stacked gate type or the split gate type, the flash memory performs the program operation or the erase operation using electrons at a floating gate. The erase operation is performed to sectors (or blocks) including a plurality of pages, or each memory cell at once.
The program operation is performed at each memory cell, or alternately at each page. For example, as shown in FIG. 1, Vt+0.4 V (where Vt is a threshold voltage of a memory cell) is applied to a control gate CG of the memory cell through the word line WL selected according to address information, 10 V is applied to a source S through a source line SL, and 0.4 V is applied to a drain D through a selected bit line BL. Then, electrons drawn to the source along an electric field generated between the drain D and the source S are tunneled to the floating gate due to the hot electron effect. As a result, the threshold voltage of the memory cell is increased. Each memory cell with an increased threshold voltage due to the program operation is determined as an off-cell in the read operation.
In this program operation, since one word line is connected to a plurality of memory cells and each memory cell is connected to a bit line, the memory cells connected to non-selected bit lines among the memory cells connected to the selected word line should be prohibited from being programmed when selectively programming one memory cell (program prohibition operation). As one of the general methods, the selected bit line (or the bit line connected to the selected memory cell) and the non-selected bit lines (or the bit lines connected to the non-selected memory cells among the memory cells connected to the selected word line) are precharged to the power supply voltage VDD and the program operation is performed to the selected memory cell.
Referring to FIG. 2 showing the conventional program operation, if a high voltage signal HVEN is activated at the time t1, a charge pump of the memory device begins to increase a high voltage VPP to the voltage level (for example, 10 V) required for the program operation. The bit lines BLS and BLN are simultaneously precharged to the power supply voltage VDD in response to the activations of signals PBLS and PBLN, which respectively precharge the selected bit line BLS and the non-selected bit lines BLN at a time t2 when a program signal PGM is activated to be at high level. In this procedure, a peak current is generated since the selected bit line BLS and the non-selected bit line BLN are precharged at once in the interval between the time t2 and time t3. In general, 1024 bit lines including one selected bit line are precharged to the power supply voltage at once and the peak current increases greatly since one memory cell block consists of at least 1024 bit lines. Further, when the bit lines are not fully charged up to the high voltage VPP even at the time t2 , the peak current is further increased since they are charged up to the high voltage VPP while the bit lines are precharged in an interval between t2 and t3.
Such a peak current is a large obstacle in interfacing terminals when a flash memory is used in a smart card for communications or personal information storage. For example, the peak current can greatly affect operational stability or reliability in a subscriber identify module card (SIM) as used in a mobile communications terminal.